Royalty Report: Semiconductors, Fabrication, Electrical & Electronics – Collection: 6602

$150.00

Curated Royalty Rate Report
Category: Technology Licenses, Created On: 2022-04-28, Record Count: 14

Description

This collection of transactions and supporting information was developed using our AI algorithm to curate similar royalty reports into a cohesive collection to support your licensing, transfer pricing or other transaction scenarios where documented royalty rates and/or deal terms are important.
Category: Technology Licenses
Created On: 2022-04-28
Record Count: 14

Primary Industries

  • Semiconductors
  • Fabrication
  • Electrical & Electronics
  • IC
  • Packaging & Containers
  • Test/Monitoring
  • Circuits
  • RAM
  • Energy Resources & Svcs

IPSCIO Report Record List

Below you will find the records curated into this collection.  This summary includes the complete licensed property description so that you can review and determine if this collection covers the topics, technology or transaction type that is relevant for your needs.  The full report will include all relevant deal data such as the royalty base, agreement date, term description, royalty rates and other deal terms.  For reference, here is a sample of a full IPSCIO curated royalty rate report: Sample Report

IPSCIO Record ID: 6602

License Grant
Austrian Licensor hereby grants to Licensee a license under Infineon Background IPR to use the to make Licensed Products and to sell and offer to sell such Licensed Products to its customers. This agreement granted a non-exclusive License to incorporate the technology developed under the Development Agreement into Licensee products based on the Stratus S200 tool platform. The License does not commence until January 1, 2014.
License Property
Intellectual Property Rights” shall mean any patents, patent rights, trademarks, service marks, registered designs, applications for any of the foregoing, copyright, unregistered design right and any other similar protected rights in any country.

Licensed Product/s shall mean any product based on the tool platform of NEXX Stratus 5200.

Pursuant to the terms of the Development Agreement we entered into with Infineon in September 2008, we have agreed to carry out the development of customized tool features, based on our Stratus S200 tool platform, and to provide Infineon with the results of this development work for use in Infineon’s manufacturing process for logic and semiconductors. Infineon will own the results of the development work other than any enhancements to the tool platform, which shall belong to us.

Field of Use
The Licensee meets the demand for smaller, high performance packages in the electronics industry, by designing, manufacturing, selling, installing and servicing highly-engineered semiconductor process equipment that automates the packaging of semiconductor devices. Advanced packaging process solutions include electrochemical deposition (ECD) systems used to deposit metal layers to plate wafer bumps or copper pillars and redistribution layers as well as fill 3D TSVs.

IPSCIO Record ID: 6727

License Grant
The Parties have agreed to the joint development of semiconductor apparatus and processes relating to plating technology for advanced packaging and integration solutions in semiconductor processing and manufacturing. The Licensor has granted a license under its intellectual property rights to develop, make, have made and sell certain products.
License Property
Packaging Technology means any process, procedure, software, or hardware tools used in the packaging of Integrated Circuit products into single-chip packages, multi-chip packages, or any other higher levels of assembly.

IPSCIO Record ID: 291104

License Grant
The Parties previously entered into three (3) technology license agreements relating to a technology known as C-4 plating technology in which certain license rights were granted to Licensee.  The Parties desire to extend the license rights previously granted.

Licensor extends the license rights granted in the C-4 Agreements for Licensee to perform Bumping on 300mm semiconductor wafers solely for Licensee only in the Dresden Facility, manufacture Licensed Products solely for Licensee only in the Dresden Facility using Bumping on 300mm semiconductor wafers, use solely for Licensee Licensed Products only in the Dresden Facility using Bumping on 300mm semiconductor wafers, sell and have sold worldwide solely under the Licensee brand name Licensed Products manufactured using Bumping on 300mm semiconductor wafers, and manufacture only in the Dresden Facility and have manufactured by Another Manufacturer for Licensee’s internal use only, any apparatus designed or modified to implement Bumping of 300mm semiconductor wafers.

Licensor grants the right to use the Licensed Technology to perform Bumping of 200mm semiconductor wafers for third parties.

The license rights extended to Licensee are nonexclusive, nontransferable and revocable.

License Property
Bumping shall have the meaning in the C-4 Plating Technology Transfer and Licensing Agreement.  Typically, Wafer bumping is an essential to flipchip or board level semiconductor packaging. Bumping is an advanced wafer level process technology where “bumps” or “balls” made of solder are formed on the wafers in a whole wafer form before the wafer is being diced into individual chips.
Field of Use
The agreement relates to the semiconductor industry.

IPSCIO Record ID: 4483

License Grant
The original Licensee entered into a related-party patent and technical support agreement with Licensor.  A US based company recently purchased Licensee and will be bound by the original licensee.
License Property
The licensed technology is used for electroplated wafer bumping and turnkey wafer level 'chip scale' packaging, together with installed and operationally qualified, high volume 200mm and 300mm electroplated wafer bumping and wafer level packaging manufacturing operations. This is 'back-end' wafer level processing technologies including wafer level CSP, electroplated lead-free and low alpha wafer bumping, fine pitch solder bumps, redistribution, and multi-layer thin film capabilities.  Flip chip is already a conventional packaging technology for microprocessors and is becoming mainstream for graphics, ASICs and chipsets.
Field of Use
The new Licensee is one of the world’s leading providers of outsourced semiconductor packaging and test services.

IPSCIO Record ID: 6726

License Grant
In connection with the development agreement Grantee is given a nonexclusive and worldwide license under Grantor Licensed Patents.  Parties have agreed to the joint development of semiconductor apparatus and processes relating to plating technology for advanced packaging and integration solutions in semiconductor processing and manufacturing.
License Property
IHS Product shall mean an Information Handling System or any instrumentality or aggregate of instrumentalities (including, without limitation, any component, subassembly, computer program or supply) designed for incorporation in an Information Handling System. Any instrumentality or aggregate of instrumentalities primarily designed for use in the fabrication (including testing) of an IHS Product shall not be considered to be an IHS Product.

Information Handling System shall mean any instrumentality or aggregate of instrumentalities primarily designed to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, measure, detect, record, reproduce, handle or utilize any form of information, intelligence or data for business, scientific, control or other purposes.

IPSCIO Record ID: 4164

License Grant
The Licensor licensed to us TCP-related technology and intellectual property rights.
License Property
Tape Carrier Package Technology (TCP) offer a high number of inputs and outputs, a thin package profile and a smaller footprint on the circuit board, without compromising performance. Key package features include surface mount technology design, fine-pitch tape format and slide carrier handling. Because of their flexibility and high number of inputs and outputs, TCPs are primarily employed either for STN-LCD or TFT-LCD driver semiconductors.
Testing of tape carrier packages. We conduct full function testing of LCD and other flat-panel display driver semiconductors with a specially designed probe handler to ensure reliable contact to the test pads on the TCP tape. We can test STN-LCD or TFT-LCD driver semiconductors with frequencies of up to 750 MHz and at voltages up to 40V. The test is performed in a temperature-controlled environment with the device in tape form. The assembled and tested LCD and other flat-panel display driver semiconductors in tape form are packed between spacer tapes together with a desiccant in an aluminum bag to avoid contact during shipment.

Assembly of tape carrier packages. TCPs use a tape-automated bonding process to connect die and tape. The printed circuit tape is shipped with a reel. The reel is then placed onto an inner lead bonder, where the LCD or other flat-panel display driver semiconductor is configured onto the printed circuit tape. The resulting TCP component consists of the device interconnected to a three-layer tape, which includes a polyamide-down carrier film, an epoxy-based adhesive layer and a metal layer. The tape metallization area of the interconnections is tin plated over a metal layer. The silicon chip and inner lead area is encapsulated with a high temperature thermoset polymer after inner lead bonding. The back face of the chip is left un-sealed for thermal connection to the printed circuit board.

Field of Use
The Licensee provides gold bumping, testing and assembly services for LCD and other flat-panel display driver semiconductors by employing tape carrier package, or TCP, chip-on-film, or COF, and chip-on-glass, or COG, technologies.

IPSCIO Record ID: 202872

License Grant
Licensor agrees to grant twenty (20) compiler tokens to the Singapore Licensee.
License Property
The licensed property is wafer manufactured at Licensee that incorporates any Licensee/Licensor 0.35um/0.25um memory compilers or wafers.

The memory compilers included are
• 0.35nm process
(i) 1 port High density compiler
• 0.25nm process
(i) 1 port High Density compiler (HD-Family)
(ii) 2 port High density compiler (HD-Family)
(iii) 1 port Register file
(iv) 2 port Register file

Field of Use
This agreement is for the semiconductor industry.

IPSCIO Record ID: 230774

License Grant
The Parties agree to jointly develop semiconductor manufacturing process technology based on Licensor’s “S” high performance technology roadmap on commercially available wafers that meet the requirements (referred to as Strategic Technology Objectives) in accordance with the schedule (hereinafter referred to as Development Schedule). The Parties agree that the process technology so developed, shall be high performance, leading edge technology and, to the extent consistent with the Strategic Technology Objectives, shall be cost efficient. Any modification to such Strategic Technology Objectives or Development Schedule requires the mutual agreement of the Parties. For the avoidance of doubt, none of the Process Development Projects shall include the development of i) Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Memory, v) SiGe Technology, vi) Chip Designs, or vii) Post-Silicon Devices.
License Property
Semiconductor Product means a component that contains an Integrated Circuit on a single or multichip module that incorporates a means of connecting those Integrated Circuits with other electronic elements (active or passive) and/or means to make external electrical connections to such elements, but which excludes any means for a user to operate the functions therein (e.g., buttons, switches, sensors).

Licensed Product means Integrated Circuits that include Bulk CMOS Information, Industry Standard Information, High Performance Device Information, SOI Device Information, or any combination thereof, other than Foundry Products.

Integrated Circuit means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, Integrated Circuit shall include charge-coupled devices (“CCDs”).

Bulk CMOS Information means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, and/or (ii) selected by Licensor either for incorporation into an Licensor Bulk CMOS process or otherwise pursuant to this agreement.

Industry Standard Information means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, or (ii) applicable to Industry Standard CMOS and selected by Licensor either for incorporation into an Licensor Industry Standard CMOS process or otherwise selected pursuant to this agreement.

High Performance Device Information means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created on substrates, not including SOI Device Information. Bulk CMOS Information or Industry Standard Information.

SOI Device Information means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created on commercially available SOI Wafers other than Bulk CMOS or Industry Standard Information.

Field of Use
This agreement pertains to the semiconductor industry.

IPSCIO Record ID: 203510

License Grant
Licensor grants a non-exclusive, perpetual, worldwide, irrevocable license to use the Bulk CMOS Information and portions of Specific Results other than those portions which Licensee uses exclusively to produce the highest performing thirty percent (30%} of wafers manufactured in the applicable technology generation (e.g. 45nm, 32nm) in any given quarter for the purpose of researching, developing, engineering and manufacturing up to one thousand (1000) 300mm wafers, other than SOI Wafers, per week in 65nm, 45nm and/or 32 nm technology, including the right to sell, market, distribute or otherwise dispose of such wafers to Third Parties, provided that such licensed wafers manufactured using the aforementioned portions of Specific Results shall not include high performance microprocessors intended for use in high performance enterprise Servers.

After September 30, 2003, Licensee may exercise the sublicensing option. If Bump Technology is established as a Process Development Project,  Licensor grants Licensee the right to disclose and sublicense the process technology developed by Licensor and Licensee under this Agreement including SOI Device Information, High Performance Device Information and Bulk CMOS and Industry Standard CMOS Information and Pre-TO Information, subject to the following AMO may sublicense no more than two (2) JMP for a maximum of a total of two (2) joint manufacturing facilities with a combined maximum of 20,000 300 mm wafers per month for such technology consumed by, or supplied to the Joint Manufacturing Partners (JMP).

License Property
The technology is leading edge semiconductor manufacturing processes.

The Licensed Product means Integrated Circuits that include Bulle CMOS Information, Industry Standard Information, High Performance Device Information (excluding eDRAM Technology), SOI Device Information (excluding eDRAM Technology), or any combination thereof, other than Foundry Products.

“Chip Design(s)” means any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that “Chip Designs” shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM macro cells and eDRAM macros) as well as such test chips themselves used for the development work of the Process Development Projects unless specifically excluded (for the avoidance of doubt, this phrase means that such structures or macros that are specifically designated as owner proprietary shall not be considered Specific Results), (iii) other product designs (including eDRAM macros) as mutually agreed by the Parties to be used as qualification vehicles in the Process Development Projects, or (iv) ESD protection devices as used in the Project Test Sites and ESD groundrules and models as defined in the Design Manual. For the avoidance of doubt, all of (i) through (iv) above shall be treated as Specific Results to the extent utilized in a Process Development Project.

“CMOS 10S” means a 90 nanometer CMOS logic fabrication process.

“Embedded DRAM” or “eDRAM” means a device that either (i) primarily carries out logic functions, and includes one or more dynamic random access memory (DRAM) cells embedded within logic circuitry on the same semiconductor substrate, or (ii) primarily carries out memory functions, and includes one or more DRAM cells in combination with a static random access memory (SRAM) array on the same semiconductor substrate (including an array of SRAM cells linked with bit lines, word lines, sense amplifiers and decoders).

“Integrated Circuit” means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, “Integrated Circuit” shall include charge-coupled devices (“CCDs”).

“Lithography” shall mean those aspects of Background Know-How and Specific Results directed to (a) process technology-dependent ground rules or process technology-dependent special rules for shapes replication as developed by the Parties for the generation of photomasks used for development and qualification of a semiconductor process technology in the Process Development Projects, (b) resolution enhancement techniques specifically created pursuant to the Process Development Projects to generate mask build data, (c) such photomasks themselves and the data files used therefor as are used in the Process Development Projects, (d) lithography process sequence as utilized in the Process Development Projects, and (e) mask data generation sequence as utilized in the Process Development Projects.

Field of Use
This agreement is for semiconductor industry.

IPSCIO Record ID: 27456

License Grant
The Company licensed certain trademarks and technology, and granted to a company headquartered in Kanagawa Prefecture, Japan the exclusive right to manufacture and sell in Japan, Korea, Taiwan, Hong Kong, China, India, the Philippines, Thailand, Vietnam, Malaysia, Singapore and Indonesia, and such other countries as the parties may agree to from time to time, products similar to those manufactured and distributed by the Company.
License Property
The Company designs, develops, manufactures, markets and services chemical mechanical planarization, or CMP, systems used in the fabrication of semiconductor devices as well as other high throughput precision surface processing systems used in the fabrication of thin film memory disk media, semiconductor wafers and general industrial components; products include polishing, grinding and lapping equipment and systems; cleaning systems; other high precision surface processing equipment; and certain other products used in its customers’ manufacturing process, including slurries.

IPSCIO Record ID: 328

License Grant
Japanese Licensor hereby grants to Licensee the exclusive License under the Patents, Technical Information and Intellectual Property Rights to manufacture, use, offer for sale, sell, import and/or lease the Products in the territory; provided, however, Licensee agrees not to manufacture any of the three Products listed in this Agreement at any time on or prior to June 30, 2006; provided further, however, that Licensee may start on the effective date to manufacture, use, offer for sale, sell, import and/or lease in the territory all subsystems related to any Products, including, but not limited to, the Nison Vesper submodule. For the avoidance of doubt, Licensor acknowledges and agrees that the License granted to Licensee under this Agreement includes the right of the Licensee to subLicense to any purchaser of the Products the right to use (but not manufacture) the Patents, Technical Information and Intellectual Property Rights.
License Property
Licensor was incorporated to, among other things, manufacture and distribute certain products and systems of Licensee in Japan in accordance with a Shareholders Agreement dated June 5, 1991.  This license is a result of Licensor buying a portion of the business of a semiconductor manufacturing equipment business and licensing back rights to Licensee.

The parties agree that the definition of Products includes subsystems related to the products (e.g. the Nison Vesper submodule) only to the extent such subsystems are incorporated in Products sold by Licensee to end-users of the Products and not to original equipment manufacturers.  Three products are covered by this agreement Spin Processor CENOTE, a single wafer wet station; Best, a wafer backside3 etcher, and Wet Station, an immersion process system.

Patent

Title
No.
number

number
Country

1
Method of recirculation of high temperature etching solution
63–248757
02–096334

1653241
Japan

2
Cleaning/ rinsing vessel for semiconductor wafer
03–350731
05–166787

2013691
Japan

3
Method for refinig etchant
05–253672
07–086260

3072876
Japan

4
Single wafer spin etching method
07–104581
08–279485

3459137
Japan

5
Etching method with hot phosphoric acid
07–216528
09–045660

3459141
Japan

6
Composition measuring method for buffered hydrofluoric acid for semiconductor wafer etching
07–163075
08–334461

N/A
Japan

7
Regeneration treatment apparatus for etchant and etching apparatus using the same
10–095836
11–293479

N/A
Japan

8
Cleaning apparatus
11–199868
2001–028356

N/A
Japan

9
Filter device with bellows damper and chemical–circulation treatment device for semiconductor wafer using the same
11–222204
2001–046815

N/A
Japan

10
Semiconductor wafer cleaning system
11–234855
2001–060574

N/A
Japan

11
Method of etching semiconductor wafer
11–271065
2001–093876

N/A
Japan

12
Device and method for etching semiconductor wafer
11–314794
2001–135611

N/A
Japan

13
Scrub cleaning device
2000–044343
2001–237209

N/A
Japan

14
Cleaning Equipment of wafer
2000–274592
2002–093764

N/A
Japan

15
Equipment and method for processing solution for semiconductor wafer
2001–009915
2002–217165

N/A
Japan

16
Wafer–cleaning device
2001–158580
2002–353183

N/A
Japan

17
The apparatus and the method of etching wafer
2002–42120
2003–243353

N/A
Japan

18
The apparatus of reclaiming etching liquid and method and apparatus of etching
2002–269405
N/A

N/A
Japan

19
The method of controlling the boiling chemical
2002–318730
2004–153164

N/A
Japan

20
The apparatus and the method of floating wafer chuck
2002–108651
2003–303871

N/A
Japan

21
The apparatus of wafer treatment and shaft
2003–47148
N/A

N/A
Japan

22
Etching method and equipment
2002–324795
2004–158746

N/A
Japan

23
Processing method and processing device before wafer inspection
2001–266653
2003–75312

N/A
Japan

24
Processing method and processing device before wafer inspection
2002–156835
2003–344243

N/A
Japan

25
Method for recirculating high–temperature etching soluthin
412444
N/A

4980017
USA

26
Method for purification of etching solution
305334
N/A

5470421
USA

Trademarks

Class of

NO
Trademark
goods
Designated goods

1 NISON
7
The apparatus of filtering recirculation etching liquid and other chemical machines and instruments

2 NISON
9
Automatic fluid– composition control machines and instruments

3 CENOTE
7
The apparatus of wafer etching, chemical machines and instruments

4 Stelna
7
The machines of chemical reaction and machines of separation, the chemical reclaiming etching apparatus, and other chemical machine and instruments.

Remark An application shall designate one or more items of goods on which the trademark is to be used, in one class of the classification of goods, prescribed by Cabinet Order.

Product
Product Name

Description

Spin Processor CENOTE
Single Wafer Wet Station

Best

                Wafer Backside Etcher

Wet Station

Immersion Process System

Field of Use
Products means any and all products, systems and subsystems now or hereafter produced by or under control of Licensee based upon the Technical Information given under this Agreement which are in the field of surface conditioning, cleaning, etch and stripping technology such as the Technical Information used in the products to this Agreement and any products, systems and subsystems to be used in the Field which will be developed, designed or invented, or otherwise acquired by Licensor in the future during the term of this Agreement.

IPSCIO Record ID: 134397

License Grant
The Licensor released the non-compete clause in the agreement for a royalty payment in the field of pre-owned equipment sales through January 2002.
License Property
The pre-owned equipment is semiconductor production equipment relating to semiconductor manufacturing tools and systems.
Field of Use
This agreement pertains to the semiconductor industry.

IPSCIO Record ID: 3514

License Grant
Under the agreements, Licensor granted to Licensee, a related party, a license to certain high-throughput combinatorial patents held or licensed by Licensor and related software to design, develop and manufacture integrated circuits, photovoltaic cells, glass coatings, light emitting diodes, organic light-emitting diodes and thin films for electronics, optical and energy applications.

The initial license grant covered technology that facilitated the Licensee's proprietary approach to accelerate research and development, innovation and time-to-market for the semiconductor and clean energy industries.

As part of the Licensee's the Licensor asset purchase transaction dated July 28, 2011, and in connection with Licensee's initial public offering, Licensee no longer has an obligation to pay licensing fees to Licensor for any period on or after January 1, 2012.  When License was executed, the Licensee's CEO was a Director of the Licensor.

License Property
Licensee has a license to approximately 326 U.S. patents and applications granted to them by Licensee that exclusively provided the right to use combinatorial methods to develop Program IP.   Program IP are the innovations that result from applying the HPC platform to design, develop and manufacture ICs, solar cells, glass coatings and glass-based devices, LEDs and thin films for electronics, optical and energy applications.

The HPC platform consists of Licensee's Tempusâ„¢ processing tools, automated characterization methods, and Informatics analysis software. The platform is purpose-built for R&D using combinatorial process systems. Combinatorial processing is a methodology for experimentation, discovery and development that employs parallel and other high-throughput experimentation, which allows R&D experimentation to be performed at speeds up to 100 times faster than conventional R&D platforms, which are optimized for manufacturing rather than for R&D. The HPC platform allows Licensee to perform up to 192 experiments on a single substrate as compared to traditional methods, which typically allow only a single experiment at a time.

IPSCIO Record ID: 449

License Grant
Licensor, who is also the CEO of Licensee, hereby grants a full exclusive, royalty-bearing license under the Licensed Know How, Copyrights, Trademarks and Computer Source Code and patents if any (hereinafter the Licensed Intellectual Property) to make, use, lease, and sell the Company's products worldwide.
License Property
The Licensed Intellectual Property hereinafter defined related to Software Source Code for Electronic Vision Products, i.e. scanners.  The Company developes and markets vision inspection solutions for the semiconductor industry.

'Scanner Products' shall mean and include any equipment, device, or apparatus intended for applications which, upon manufacture includes, or the manufacture of which employs, any future invention or inventions resulting from the use of any of the Licensed Know How or the Intellectual Property or which includes when sold, leased, or put into use, or the use of which employs when put into use, any invention or future inventions of the Licensed Know How, and any future products developed by Scanner during the term of this agreement.

The trademark Cyclops 2000-3D and any derivatives thereof shall be included in the License Grant.

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