Royalty Report: Semiconductors, Fabrication, Packaging & Containers – Collection: 4198

License Grant

Licensor agreed to assign to Licensee, a subsidiary,  all of our rights, title and interest in certain patents and patent applications relating to probe array design, probe array manufacturing techniques, probe array layouts, or probe array packaging techniques. We also granted certain rights and licenses.

Field of Use

The agreement provides that Licensee shall not use chips or wafers produced.

License Grant

The Licensee entered into an assignment of patent and intellectual rights Agreement with an Individual, the Licensor, a retired employee who was formerly our Vice-President. As part of an employment Agreement, the Licensor assigned to us all rights and interests to five U.S. Provisional Patent Applications owned by him.

Those applications subsequently resulted in three issued U.S. Patents assigned to us covering various chip package stacking techniques. In consideration for this assignment, the Licensor receives a royalty on the gross sales revenues, if any, of any products incorporating the technology of these patent assignments for the lifetime of these patents.

License Grant

The Parties previously entered into three (3) technology license agreements relating to a technology known as C-4 plating technology in which certain license rights were granted to Licensee.  The Parties desire to extend the license rights previously granted.

Licensor extends the license rights granted in the C-4 Agreements for Licensee to perform Bumping on 300mm semiconductor wafers solely for Licensee only in the Dresden Facility, manufacture Licensed Products solely for Licensee only in the Dresden Facility using Bumping on 300mm semiconductor wafers, use solely for Licensee Licensed Products only in the Dresden Facility using Bumping on 300mm semiconductor wafers, sell and have sold worldwide solely under the Licensee brand name Licensed Products manufactured using Bumping on 300mm semiconductor wafers, and manufacture only in the Dresden Facility and have manufactured by Another Manufacturer for Licensee’s internal use only, any apparatus designed or modified to implement Bumping of 300mm semiconductor wafers.

Licensor grants the right to use the Licensed Technology to perform Bumping of 200mm semiconductor wafers for third parties.

The license rights extended to Licensee are nonexclusive, nontransferable and revocable.

License Property

Bumping shall have the meaning in the C-4 Plating Technology Transfer and Licensing Agreement.  Typically, Wafer bumping is an essential to flipchip or board level semiconductor packaging. Bumping is an advanced wafer level process technology where “bumps” or “balls” made of solder are formed on the wafers in a whole wafer form before the wafer is being diced into individual chips.

Field of Use

The agreement relates to the semiconductor industry.

License Grant

The original Licensee entered into a related-party patent and technical support agreement with Licensor.  A US based company recently purchased Licensee and will be bound by the original licensee.

License Property

The licensed technology is used for electroplated wafer bumping and turnkey wafer level 'chip scale' packaging, together with installed and operationally qualified, high volume 200mm and 300mm electroplated wafer bumping and wafer level packaging manufacturing operations. This is 'back-end' wafer level processing technologies including wafer level CSP, electroplated lead-free and low alpha wafer bumping, fine pitch solder bumps, redistribution, and multi-layer thin film capabilities.  Flip chip is already a conventional packaging technology for microprocessors and is becoming mainstream for graphics, ASICs and chipsets.

Field of Use

The new Licensee is one of the world’s leading providers of outsourced semiconductor packaging and test services.

License Grant

Licensor grants a non-exclusive, perpetual, worldwide, irrevocable license to use the Bulk CMOS Information and portions of Specific Results other than those portions which Licensee uses exclusively to produce the highest performing thirty percent (30%} of wafers manufactured in the applicable technology generation (e.g. 45nm, 32nm) in any given quarter for the purpose of researching, developing, engineering and manufacturing up to one thousand (1000) 300mm wafers, other than SOI Wafers, per week in 65nm, 45nm and/or 32 nm technology, including the right to sell, market, distribute or otherwise dispose of such wafers to Third Parties, provided that such licensed wafers manufactured using the aforementioned portions of Specific Results shall not include high performance microprocessors intended for use in high performance enterprise Servers.

After September 30, 2003, Licensee may exercise the sublicensing option. If Bump Technology is established as a Process Development Project,  Licensor grants Licensee the right to disclose and sublicense the process technology developed by Licensor and Licensee under this Agreement including SOI Device Information, High Performance Device Information and Bulk CMOS and Industry Standard CMOS Information and Pre-TO Information, subject to the following AMO may sublicense no more than two (2) JMP for a maximum of a total of two (2) joint manufacturing facilities with a combined maximum of 20,000 300 mm wafers per month for such technology consumed by, or supplied to the Joint Manufacturing Partners (JMP).

License Property

The technology is leading edge semiconductor manufacturing processes.

The Licensed Product means Integrated Circuits that include Bulle CMOS Information, Industry Standard Information, High Performance Device Information (excluding eDRAM Technology), SOI Device Information (excluding eDRAM Technology), or any combination thereof, other than Foundry Products.

“Chip Design(s)” means any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that “Chip Designs” shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM macro cells and eDRAM macros) as well as such test chips themselves used for the development work of the Process Development Projects unless specifically excluded (for the avoidance of doubt, this phrase means that such structures or macros that are specifically designated as owner proprietary shall not be considered Specific Results), (iii) other product designs (including eDRAM macros) as mutually agreed by the Parties to be used as qualification vehicles in the Process Development Projects, or (iv) ESD protection devices as used in the Project Test Sites and ESD groundrules and models as defined in the Design Manual. For the avoidance of doubt, all of (i) through (iv) above shall be treated as Specific Results to the extent utilized in a Process Development Project.

“CMOS 10S” means a 90 nanometer CMOS logic fabrication process.

“Embedded DRAM” or “eDRAM” means a device that either (i) primarily carries out logic functions, and includes one or more dynamic random access memory (DRAM) cells embedded within logic circuitry on the same semiconductor substrate, or (ii) primarily carries out memory functions, and includes one or more DRAM cells in combination with a static random access memory (SRAM) array on the same semiconductor substrate (including an array of SRAM cells linked with bit lines, word lines, sense amplifiers and decoders).

“Integrated Circuit” means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, “Integrated Circuit” shall include charge-coupled devices (“CCDs”).

“Lithography” shall mean those aspects of Background Know-How and Specific Results directed to (a) process technology-dependent ground rules or process technology-dependent special rules for shapes replication as developed by the Parties for the generation of photomasks used for development and qualification of a semiconductor process technology in the Process Development Projects, (b) resolution enhancement techniques specifically created pursuant to the Process Development Projects to generate mask build data, (c) such photomasks themselves and the data files used therefor as are used in the Process Development Projects, (d) lithography process sequence as utilized in the Process Development Projects, and (e) mask data generation sequence as utilized in the Process Development Projects.

Field of Use

This agreement is for semiconductor industry.

License Grant

The Company agrees to grant to a Korean company the right to a processes involving technology, equipment design, and other intangible assets and property rights of value, all of which are useful with respect to the manufacture of Silicon Wafers.

License Property

The Company has developed over the years and possesses processes involving technology, equipment design, and other intangible assets and property rights of value, all of which are useful with respect to the manufacture of Silicon Wafers (as hereinafter defined) and certain value added features such as epitaxial layers.

Field of Use

Field of this Agreement means Silicon Wafers and processes, apparatus, equipment, and materials useful in producing Silicon Wafers consistent with the commercial requirements of PHC.

The Field of this Agreement shall not include processes, apparatus, equipment, and materials useful in producing polycrystal Silicon.