Category: Technology Licenses
Created On: 2022-04-28
Record Count: 6
- Packaging & Containers
IPSCIO Report Record List
Below you will find the records curated into this collection. This summary includes the complete licensed property description so that you can review and determine if this collection covers the topics, technology or transaction type that is relevant for your needs. The full report will include all relevant deal data such as the royalty base, agreement date, term description, royalty rates and other deal terms. For reference, here is a sample of a full IPSCIO curated royalty rate report: Sample Report
IPSCIO Record ID: 4198
IPSCIO Record ID: 1079
Those applications subsequently resulted in three issued U.S. Patents assigned to us covering various chip package stacking techniques. In consideration for this assignment, the Licensor receives a royalty on the gross sales revenues, if any, of any products incorporating the technology of these patent assignments for the lifetime of these patents.
IPSCIO Record ID: 291104
Licensor extends the license rights granted in the C-4 Agreements for Licensee to perform Bumping on 300mm semiconductor wafers solely for Licensee only in the Dresden Facility, manufacture Licensed Products solely for Licensee only in the Dresden Facility using Bumping on 300mm semiconductor wafers, use solely for Licensee Licensed Products only in the Dresden Facility using Bumping on 300mm semiconductor wafers, sell and have sold worldwide solely under the Licensee brand name Licensed Products manufactured using Bumping on 300mm semiconductor wafers, and manufacture only in the Dresden Facility and have manufactured by Another Manufacturer for Licenseeâ€™s internal use only, any apparatus designed or modified to implement Bumping of 300mm semiconductor wafers.
Licensor grants the right to use the Licensed Technology to perform Bumping of 200mm semiconductor wafers for third parties.
The license rights extended to Licensee are nonexclusive, nontransferable and revocable.
IPSCIO Record ID: 4483
IPSCIO Record ID: 203510
After September 30, 2003, Licensee may exercise the sublicensing option. If Bump Technology is established as a Process Development Project, Licensor grants Licensee the right to disclose and sublicense the process technology developed by Licensor and Licensee under this Agreement including SOI Device Information, High Performance Device Information and Bulk CMOS and Industry Standard CMOS Information and Pre-TO Information, subject to the following AMO may sublicense no more than two (2) JMP for a maximum of a total of two (2) joint manufacturing facilities with a combined maximum of 20,000 300 mm wafers per month for such technology consumed by, or supplied to the Joint Manufacturing Partners (JMP).
The Licensed Product means Integrated Circuits that include Bulle CMOS Information, Industry Standard Information, High Performance Device Information (excluding eDRAM Technology), SOI Device Information (excluding eDRAM Technology), or any combination thereof, other than Foundry Products.
â€œChip Design(s)â€ means any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that â€œChip Designsâ€ shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM macro cells and eDRAM macros) as well as such test chips themselves used for the development work of the Process Development Projects unless specifically excluded (for the avoidance of doubt, this phrase means that such structures or macros that are specifically designated as owner proprietary shall not be considered Specific Results), (iii) other product designs (including eDRAM macros) as mutually agreed by the Parties to be used as qualification vehicles in the Process Development Projects, or (iv) ESD protection devices as used in the Project Test Sites and ESD groundrules and models as defined in the Design Manual. For the avoidance of doubt, all of (i) through (iv) above shall be treated as Specific Results to the extent utilized in a Process Development Project.
â€œCMOS 10Sâ€ means a 90 nanometer CMOS logic fabrication process.
â€œEmbedded DRAMâ€ or â€œeDRAMâ€ means a device that either (i) primarily carries out logic functions, and includes one or more dynamic random access memory (DRAM) cells embedded within logic circuitry on the same semiconductor substrate, or (ii) primarily carries out memory functions, and includes one or more DRAM cells in combination with a static random access memory (SRAM) array on the same semiconductor substrate (including an array of SRAM cells linked with bit lines, word lines, sense amplifiers and decoders).
â€œIntegrated Circuitâ€ means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, â€œIntegrated Circuitâ€ shall include charge-coupled devices (â€œCCDsâ€).
â€œLithographyâ€ shall mean those aspects of Background Know-How and Specific Results directed to (a) process technology-dependent ground rules or process technology-dependent special rules for shapes replication as developed by the Parties for the generation of photomasks used for development and qualification of a semiconductor process technology in the Process Development Projects, (b) resolution enhancement techniques specifically created pursuant to the Process Development Projects to generate mask build data, (c) such photomasks themselves and the data files used therefor as are used in the Process Development Projects, (d) lithography process sequence as utilized in the Process Development Projects, and (e) mask data generation sequence as utilized in the Process Development Projects.
IPSCIO Record ID: 27206
The Field of this Agreement shall not include processes, apparatus, equipment, and materials useful in producing polycrystal Silicon.