Created On: 2020-07-15
Record Count: 12
- Computers & Office Equipment
IPSCIO Report Record List
Below you will find the records curated into this collection. This summary includes the complete licensed property description so that you can review and determine if this collection covers the topics, technology or transaction type that is relevant for your needs. The full report will include all relevant deal data such as the royalty base, agreement date, term description, royalty rates and other deal terms. For reference, here is a sample of a full IPSCIO curated royalty rate report: Sample Report
IPSCIO Record ID: 29267
IPSCIO Record ID: 3243
IPSCIO Record ID: 203510
After September 30, 2003, Licensee may exercise the sublicensing option. If Bump Technology is established as a Process Development Project, Licensor grants Licensee the right to disclose and sublicense the process technology developed by Licensor and Licensee under this Agreement including SOI Device Information, High Performance Device Information and Bulk CMOS and Industry Standard CMOS Information and Pre-TO Information, subject to the following: AMO may sublicense no more than two (2) JMP for a maximum of a total of two (2) joint manufacturing facilities with a combined maximum of 20,000 300 mm wafers per month for such technology consumed by, or supplied to the Joint Manufacturing Partners (JMP).
The Licensed Product means Integrated Circuits that include Bulle CMOS Information, Industry Standard Information, High Performance Device Information (excluding eDRAM Technology), SOI Device Information (excluding eDRAM Technology), or any combination thereof, other than Foundry Products.
â€œChip Design(s)â€ means any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that â€œChip Designsâ€ shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM macro cells and eDRAM macros) as well as such test chips themselves used for the development work of the Process Development Projects unless specifically excluded (for the avoidance of doubt, this phrase means that such structures or macros that are specifically designated as owner proprietary shall not be considered Specific Results), (iii) other product designs (including eDRAM macros) as mutually agreed by the Parties to be used as qualification vehicles in the Process Development Projects, or (iv) ESD protection devices as used in the Project Test Sites and ESD groundrules and models as defined in the Design Manual. For the avoidance of doubt, all of (i) through (iv) above shall be treated as Specific Results to the extent utilized in a Process Development Project.
â€œCMOS 10Sâ€ means a 90 nanometer CMOS logic fabrication process.
â€œEmbedded DRAMâ€ or â€œeDRAMâ€ means a device that either (i) primarily carries out logic functions, and includes one or more dynamic random access memory (DRAM) cells embedded within logic circuitry on the same semiconductor substrate, or (ii) primarily carries out memory functions, and includes one or more DRAM cells in combination with a static random access memory (SRAM) array on the same semiconductor substrate (including an array of SRAM cells linked with bit lines, word lines, sense amplifiers and decoders).
â€œIntegrated Circuitâ€ means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, â€œIntegrated Circuitâ€ shall include charge-coupled devices (â€œCCDsâ€).
â€œLithographyâ€ shall mean those aspects of Background Know-How and Specific Results directed to (a) process technology-dependent ground rules or process technology-dependent special rules for shapes replication as developed by the Parties for the generation of photomasks used for development and qualification of a semiconductor process technology in the Process Development Projects, (b) resolution enhancement techniques specifically created pursuant to the Process Development Projects to generate mask build data, (c) such photomasks themselves and the data files used therefor as are used in the Process Development Projects, (d) lithography process sequence as utilized in the Process Development Projects, and (e) mask data generation sequence as utilized in the Process Development Projects.
IPSCIO Record ID: 27937
2.1K', VTO, GAMMA, DW, DL and NSUB for all types of MOSFET devices used by the process.
2.2SPICE LEVEL 3 MOSFET models (DC and AC parameters) for all types of MOSFET devices used by the process.
2.3Measured IDS-VDS curves for all types of MOSFET devices used by the process including (a) a large square device and (b) an average width, typical length device.
2.4Measured ring oscillator performance for all operating conditions plus an accurate schematic for the ring oscillator.
2.5 Junction depths for the tub (s) ana n+/p+ diffusions.
2.6 Junction breakdown voltages for the tub (s) and n+/p+ diffusions.
2.7 MOSFET punch-through voltage characteristics.
2.8 Process cross-section including dielectric material descriptions,permitivities, thickness and interconnect layer thickness.
2.9 Resistance characteristics of interconnect layers and interlayer contacts.
2.10 Capacitance of minimum width conductor layers per unit length for various conditions of neighboring conductor layers (i.e. metal 1 over ubstrate, Metal I over substrate and covered by Metal 2, Metal 2 over Metal 1, etc. for the cases where there are adjacent tracks with typical layer to layer spacing).
2.11 Capacitance values for (a) the wordline per 'In' cells, (b) the entirebitline and (c) the memory cell.
2.12 DC and AC Metal migration guidelines.
2.13 Latch-up prevention guidelines.
2.14 Layout cell of a proven ESD protection structure.
2.15 Test wafer with sample transistors (if available).
3.0 GEOMETRICAL DEFINITION OF THE PROCESS:
3.1 A complete list of all layer names with layer definitions and numbering convention.
3.2 A complete set of geometrical design rules (array and periphery rules).
3.3 A list highlighting the unusual geometrical design rules which require more involved DRC checking procedures.
3.4 A diagram showing which layers are connected by which contacts.
3.5 Seal ring geometric design rules.
3.6 Minimum acceptable layout grid size.
IPSCIO Record ID: 211899
Licensor grants a worldwide, non-exclusive, non-transferable, non-assignable license under all Intellectual Property Rights to manufacture, have manufactured, use, offer for sale, import and sell Memory Sticks.
Licensor grants a worldwide, non-exclusive, non-transferable, non-assignable license under all Licensor Intellectual Property Rights to manufacture, have manufactured, use, offer for sale, import and sell High-Speed Memory Sticks.
Smart Media means a flash memory storage device that meets the Smart Media Specifications.
Flash Controller means a device within Flash Card Products (whether implemented in firmware, hardware and/or software) that controls the operation of a memory within such Flash Card Products.
Flash Card Products means a Flash Memory System on a card having a connector that attaches it to a host system.
Flash Memory System means an integrated circuit memory system that contains one or more interconnected flash memory devices or flash memory integrated circuits, and in-system control, I/O and other support circuit(s) that are interconnected with the flash memory devices or flash memory integrated circuits and necessary to the operation of the memory system.
IPSCIO Record ID: 2151
IPSCIO Record ID: 203531
The Product means any product using the Technology and/or Licensors Improvements in semiconductor devices that incorporate embedded nonvolatile ferroelectric memory, the Embedded Products and/or semiconductor devices that combine ferroelectric memory with RF/ID analog circuitry in a single chip Ferroelectric RF/ID Products. In no case will the Product be deemed to include standard, nonvolatile ferroelectric semiconductor memory devices.
The Technology means that certain thin-film ferroelectric technology developed and/or owned by Licensor or as to which Licensor has the right to grant a license to Licensee without payment of any compensation to third parties except Licensees employees or Subsidiaries, and which consists of technology pertaining to the manufacture and production of standard, nonvolatile, random access semiconductor memory devices that utilize binary polarization states on the hysteresis curve of ferroelectric material; and, technology pertaining to the material and process for the formation of ferroelectric film, which may be developed and/or owned by Licensor, including all technology and inventions claimed in Licensors patents.
The patent relates to, but is not necessarily limited to Self restoring ferroelectric memory.
IPSCIO Record ID: 751
Licensor has also been subject to an investigation in the European Union. Licensee was not a party to that investigation, but has recently sought to intervene in the appeal of the investigation.
As a result of Licensor's commitments to resolve that investigation, for a period of five years from the date of the resolution, Licensor must now provide a License to memory controller manufacturers, sellers, and/or companies that integrate memory controllers into other products.
The parties have not signed a release of liability for past damages, nor dismissed any outstanding litigation between the parties. The terms of the License Agreement are per the agreement that licensor offers as part of its commitment with the European Commission.
IPSCIO Record ID: 211882
– to make Licensees Licensed Products only in Singapore and one Licensee Elected Country;
– to use, import, and lease, offer for sale, sell or otherwise transfer Licensees Licensed Products worldwide;
– to use any apparatus in the manufacture or testing of Licensee Licensed Products and to practice any method or process in such manufacture or testing of Licensees Licensed Products; and
– to have Licensees Licensed Products made in whole or in part by another manufacturer for the use and/or lease, offer for sale, sale or other transfer by Licensee only when the designs and specifications for such Licensees Licensed Products were provided by Licensee to the other manufacturer, whether developed by Licensee or received by Licensee from customers to whom the Licensed Products are to be sold.
Semiconductor Apparatus shall mean Semiconductor Material, Semiconductor Device, Semiconductor Circuit, Integrated Circuit and/or Semiconductor Memories and any combination of such apparatus with other such apparatus.
'Integrated Circuit' shall mean an integral unit including a plurality of active and/or passive circuit elements formed at least in part of Semiconductor Material and associated on, or in, one substrate comprising the first level of packaging for such elements; such unit forming or contributing to the formation of a circuit for performing electrical or electronic functions.
'Semiconductor Circuit' shall mean a circuit in which one or more Semiconductor Devices are interconnected in one or more paths (including passive circuit elements, if any) for performing fundamental electrical or electronic functions and, if provided therewith, housing and/or supporting means therefor.
'Semiconductor Device' shall mean a device and any material therefor, including but not limited to device structures such as transistors, diodes, capacitors, resistors, conductors and dielectrics, comprising a body of one or more Semiconductor Materials and one or more electrodes associated therewith and, if provided therewith, housing and/or supporting means therefor.
'Semiconductor Material' shall mean any material whose conductivity is intermediate to that of metals and insulators at room temperature and whose conductivity, over some temperature range, increases with increases in temperature. Such materials shall include, but not be limited to, refined products, reaction products, reduced products, mixtures and compounds.
'Semiconductor Memory' shall mean any instrumentality or aggregate of instrumentalities, which instrumentality or aggregate is designed only for storing digital information, intelligence or data by selectively setting or presetting detectable states in Semiconductor Material forming at least a part of such instrumentality or aggregate, such instrumentality or aggregate may include powering means and auxiliary and/or support circuits (such as regeneration means, true-complement generations means, address decoding means, sensing means and selection means) to control the flow of such information, intelligence or data into and out of such Semiconductor Memory.
IPSCIO Record ID: 25950
b. EEC Patent File No. 939186441
c. Japan Patent File No. 505547/1994
Magram(TM) memory is the world's first memory to combine all the positive attributes of existing memory technologies w combine non-volatility (retains information even after being shut off) and random read/write access (fast speed), MAGRAM offers a superior memory solution for computers, diagnostic tools, medical equipment, automobiles, and a host of othositive attributes found in various other digital memory technologies including low power consumption, low ceing able to use your computer the instant you turn it on rather than having to wait for it to boot up.
IPSCIO Record ID: 215225
The Japanese Licensor grants to Chinese Licensee a non-transferable, non-exclusive, worldwide license to use Licensors Process Technology, Licensors Product Design and Licensors IPR incorporated or embodied in Licensors Process Technology and Licensors Product Design, to manufacture Licensed Products at Licensees own facilities and to market and sell such manufactured Licensed Products.
Licensor Product Design shall mean the product design data for Licensed Products which is owned or developed by Licensor, which Licensor has the right to grant a license to Licensee without payment of any compensation to third parties, and which is described in the Deliverables.
The Licensed Products shall mean certain 64Mbit synchronous dynamic random-access memory (SDRAM) devices using Licensor Process Technology and Licensor Product Design whether in a die form or in a wafer form.
IPSCIO Record ID: 223146
As between the parties, Licensor exclusively shall have all right, title and interest including all patent rights, copyrights, trade secret rights, mask work rights and other rights throughout the world (collectively Intellectual Property Rights) in any inventions, intellectual property, trademarks, works-of-authorship, mask works, ideas or information made or conceived or reduced to practice by Licensor or by Licensor jointly with Licensee and/or third parties in the course of development of the Compilers.
As between the parties, Licensee exclusively shall have all Intellectual Property Rights in (a) any Licensee Deliverables that exist prior to the Effective Date and (b) any inventions, intellectual property, trademarks, works-of-authorship, mask works, ideas or information made or conceived or reduced to practice by Licensee or by Licensee jointly with Licensor and/or third parties in the course of development of the Licensee Deliverables.
2 Port Register File
Single Port SRAM (High Density)
Dual Port SRAM (High Density)
ROM (via 2/3)
Single Port SRAM (High Speed)
Dual Port SRAM (High Speed)
STAR HS-512k Single Port
STAR HS-512k Dual Port
STAR Memory System
Licensee Deliverables. Licensee agrees to provide Licensor early access to the technical information for use by Licensor solely in connection with developing the Compilers as set forth in this Agreement.
NOVeA, which can be reprogrammed numerous times, is designed for integration into system-on-chip (SoC) applications. It is the first non-volatile, electrically alterable embedded memory solution that can be produced using standard logic processes. Most embedded non-volatile memory solutions require special process technology that adds steps and photomasks to fabrication, which increases costs and delivery time. Since NOVeA can be manufactured by using a standard logic process, additional process steps and masks are not necessary, thereby reducing costs and delivery time. By employing sub-micron geometries, NOVeA technology can help reduce overall system size, lower power consumption and increase performance.