Royalty Report: Semiconductors, IC, Fabrication – Collection: 27308

License Grant

The Company grants worldwide, nontransferable, nonexclusive and royalty-free license to Japanese Licensee of the ProASIC Technology for the development, modification, manufacturing, use and sale by Rohm of Standard ProASIC Products down to 0.35 micron with no limitation on density.

License Property

The Company has developed proprietary ProASIC Technology and has applied this ProASIC Technology in the design, manufacture, marketing and selling of its Standard ProASIC Products and licensing the ProASIC Technology.

'ASICMAKER' means the proprietary hardware programmer developed by Gatefield for programming GateField ProASIC Products. 'EMBEDDED APPLICATIONS' means the integration of GateField's ProASIC Technology as a subset of a silicon device in the same chip.

'GATEFIELD PROASIC TECHNOLOGY' or 'PROASIC TECHNOLOGY' means the proprietary ProASIC technology developed and owned by GateField including the architecture, switch cell design and operation, programming logic, analog and high voltage circuit design, simulation, verification and testing, and methodologies, but excluding all software except for the architectural file generation software which shall be included.

'GATEFIELD'S CURRENT PROASIC PRODUCTS' means GateField's standard field programmable gate array GF100K, GF250F and GF260F Product families utilizing GateField ProASIC technology as specified in GateField's current product list.

ProASIC Product or ProASIC Technology means the proprietary ProASIC technology developed and owned by Licensor including the architecture, switch cell design and operation, programming logic, analog and high voltage circuit design, simulation, verification and testing, and methodologies, but excluding all software except for the architectural file generation software which shall be included.

ProASIC Chip on Chip Products means the application of Licensor's Standard ProASIC Products with other silicon products directly placed on the mother chip utilizing Rohm's Chip on Chip packaging technology as developed by Rohm including, but not limited to the drawing attached hereto as Attachment A, as an example.

ProASIC Technology on the chip to the total chip area for any Embedded Applications; application specific integrated circuit ('ASIC') technology; ProASIC–are based on two proprietary and patented technologies a flash-based switching element and a fine-grained, gate array-like ProASIC architecture.

The Company believes that the principal advantages of its products over alternative SRAM-based and antifuse devices are smaller chip size for the same geometries; reprogrammability and non-volatility; and the ability to use a standard electronic design automation (EDA) ASIC design flow.

Field of Use

Licensee shall have the right to market and sell the Standard ProASIC Products, Version 4p2 ASICmaster Software Licenses and ASICmaker under the ProASIC trademark.  Licensee agrees to use the ProASIC trademark on all Standard ProASIC Products, ASICmaker, Embedded Applications, ProASIC Chip on Chip Products and copies of the Version 4p2  ASICmaster Software, including all documentation and collateral material.

License Grant

For the technology, Licensor shall grant a worldwide, personal, non-exclusive, non-transferable, non-assignable and revocable right and license to use, without the right to sublicense, transfer or convey such rights, in whole or in part, Licensors Technology, for the purposes of designing, modifying,   manufacturing, having manufactured, marketing, selling and otherwise disposing of integrated circuits which embody or are based upon part or all of Licensor Technology licensed by Licensor to Licensee and implemented in Designated Process Technology and which are not pin-compatible with Licensor Chips, in Licensee products, as components or Modules.

For the software, Licensor shall grant a world-wide, personal, non-exclusive, non-transferable, non-sublicenseable, non-assignable and revocable right and license, without any right to market, sublicense or distribute, to use, copy, and modify for Internal Use only and only with Licensor Chips in Designated Process Technology and/or Licensor Systems,  certain Licensor Source Code Software as set forth on the Source Code Use License Agreement.

Licensor shall grant a world-wide, personal, non-exclusive, non-transferable, fee-bearing, non assignable and revocable right and license to use for Internal Use and for sublicensing, copy for  Internal Use and for sublicensing, market, grant non-exclusive sublicenses for use and distribute  certain Licensor Binary Software,  as set forth on the Binary Software License Agreement all for use  only with Licensee Chips in Designated Process Technology and/or Licensor-based Systems.

For the Architecture License Software, Licensor shall grant a worldwide, personal, non-exclusive, non-transferable, non-sublicenseable, non-assignable and revocable right and license without any right to market, distribute or sublicense, to use, copy and modify, all for Internal Use only and only with Licensor Systems, certain Licensor Architecture License Software.

For Documentation rights, Licensor shall  grant a worldwide, personal, non-exclusive, fully-paid, non-transferable, non-assignable and revocable right and license, to use, modify, copy and distribute,  all for Internal Use only, without any right to market, copy or distribute outside of Licensee, Licensee Architecture License Documentation as set forth.

License Property

The Designate Process Technology means any technology for the design and manufacture of integrated circuit products that incorporates a type of circuit structure containing both p-channel and  n-channel MOS devices on the same silicon substrate (CMOS OR Bi-CMOS).

The licensed property includes Instruction Set and System Performance Simulator (SABLE), and Architecture Specification (superscalar) R4000 and R5000.

MIPS ARCHITECTURE – means the organization, structure, and content of any CPU or CPU support chips, or portions thereof, as designed and enhanced by MIPS, including but not limited to, MIPS Instruction Set (for example, the architecture set forth in the book entitled, MIPS RISC ARCHITECTURE) and interface specifications.

Field of Use

This agreement is for the integrated circuit industry.

License Grant

Licensor grants to Licensee, for Permitted Applications only, a worldwide, nontransferable, and nonsublicensable right to use, sell and otherwise incorporate Technology provided, however, that Licensee shall have the right to sublicense the Technology to an Alabama limited liability company and an Affiliate, for use in Permitted Applications and otherwise under the terms of this Agreement.

License Property

Technology shall mean all of Licensor's Split Bridge Technology, including current split bridge ASIC chip commonly known as 'Merlin' and ASIC split bridge chips currently under development by Licensor with LSI Logic or developed in the future. This further includes all related intellectual property and Split Bridge Chip intellectual property including without limitation software, patents and patents pending (including, without limitations, the Pending Patents), trade secrets, ASIC chips and related IP blocks, designs, specifications, and any future enhancements, modifications, variations thereto, and all intellectual property associated with the adaptation of cables and connectors adapted for use with Split Bridge Chips and technology and future generations of any of the above.

'Split Bridge Technology' is the technology which allows a main computer PCI bus to be extended to a remote location by connecting two proprietary Split Bridge Chips with a high speed cable, and includes all of the above.

License Grant

Licensor grants a non-exclusive, perpetual, worldwide, irrevocable license to use the Bulk CMOS Information and portions of Specific Results other than those portions which Licensee uses exclusively to produce the highest performing thirty percent (30%} of wafers manufactured in the applicable technology generation (e.g. 45nm, 32nm) in any given quarter for the purpose of researching, developing, engineering and manufacturing up to one thousand (1000) 300mm wafers, other than SOI Wafers, per week in 65nm, 45nm and/or 32 nm technology, including the right to sell, market, distribute or otherwise dispose of such wafers to Third Parties, provided that such licensed wafers manufactured using the aforementioned portions of Specific Results shall not include high performance microprocessors intended for use in high performance enterprise Servers.

After September 30, 2003, Licensee may exercise the sublicensing option. If Bump Technology is established as a Process Development Project,  Licensor grants Licensee the right to disclose and sublicense the process technology developed by Licensor and Licensee under this Agreement including SOI Device Information, High Performance Device Information and Bulk CMOS and Industry Standard CMOS Information and Pre-TO Information, subject to the following AMO may sublicense no more than two (2) JMP for a maximum of a total of two (2) joint manufacturing facilities with a combined maximum of 20,000 300 mm wafers per month for such technology consumed by, or supplied to the Joint Manufacturing Partners (JMP).

License Property

The technology is leading edge semiconductor manufacturing processes.

The Licensed Product means Integrated Circuits that include Bulle CMOS Information, Industry Standard Information, High Performance Device Information (excluding eDRAM Technology), SOI Device Information (excluding eDRAM Technology), or any combination thereof, other than Foundry Products.

“Chip Design(s)” means any design of one or more Integrated Circuits and/or Semiconductor Products, including (by way of example and not limitation) random access memory (RAM)s, read only memory (ROM)s, microprocessors, ASICs and other logic designs, and analog circuitry; provided, however, that “Chip Designs” shall not include (i) alignment marks or test structures and associated layout and data used in the Process Development Projects for process development, (ii) process kerf test structures, layout, and data of the test chip(s) (including SRAM macro cells and eDRAM macros) as well as such test chips themselves used for the development work of the Process Development Projects unless specifically excluded (for the avoidance of doubt, this phrase means that such structures or macros that are specifically designated as owner proprietary shall not be considered Specific Results), (iii) other product designs (including eDRAM macros) as mutually agreed by the Parties to be used as qualification vehicles in the Process Development Projects, or (iv) ESD protection devices as used in the Project Test Sites and ESD groundrules and models as defined in the Design Manual. For the avoidance of doubt, all of (i) through (iv) above shall be treated as Specific Results to the extent utilized in a Process Development Project.

“CMOS 10S” means a 90 nanometer CMOS logic fabrication process.

“Embedded DRAM” or “eDRAM” means a device that either (i) primarily carries out logic functions, and includes one or more dynamic random access memory (DRAM) cells embedded within logic circuitry on the same semiconductor substrate, or (ii) primarily carries out memory functions, and includes one or more DRAM cells in combination with a static random access memory (SRAM) array on the same semiconductor substrate (including an array of SRAM cells linked with bit lines, word lines, sense amplifiers and decoders).

“Integrated Circuit” means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, “Integrated Circuit” shall include charge-coupled devices (“CCDs”).

“Lithography” shall mean those aspects of Background Know-How and Specific Results directed to (a) process technology-dependent ground rules or process technology-dependent special rules for shapes replication as developed by the Parties for the generation of photomasks used for development and qualification of a semiconductor process technology in the Process Development Projects, (b) resolution enhancement techniques specifically created pursuant to the Process Development Projects to generate mask build data, (c) such photomasks themselves and the data files used therefor as are used in the Process Development Projects, (d) lithography process sequence as utilized in the Process Development Projects, and (e) mask data generation sequence as utilized in the Process Development Projects.

Field of Use

This agreement is for semiconductor industry.

License Grant

The Parties agree to jointly develop semiconductor manufacturing process technology based on Licensor’s “S” high performance technology roadmap on commercially available wafers that meet the requirements (referred to as Strategic Technology Objectives) in accordance with the schedule (hereinafter referred to as Development Schedule). The Parties agree that the process technology so developed, shall be high performance, leading edge technology and, to the extent consistent with the Strategic Technology Objectives, shall be cost efficient. Any modification to such Strategic Technology Objectives or Development Schedule requires the mutual agreement of the Parties. For the avoidance of doubt, none of the Process Development Projects shall include the development of i) Proprietary Tools, ii) Packaging Technology, iii) Mask Fabrication and Photoresist Technology, iv) Memory, v) SiGe Technology, vi) Chip Designs, or vii) Post-Silicon Devices.

License Property

Semiconductor Product means a component that contains an Integrated Circuit on a single or multichip module that incorporates a means of connecting those Integrated Circuits with other electronic elements (active or passive) and/or means to make external electrical connections to such elements, but which excludes any means for a user to operate the functions therein (e.g., buttons, switches, sensors).

Licensed Product means Integrated Circuits that include Bulk CMOS Information, Industry Standard Information, High Performance Device Information, SOI Device Information, or any combination thereof, other than Foundry Products.

Integrated Circuit means an integral unit formed on a semiconductor substrate including a plurality of active and/or passive circuit elements formed at least in part of semiconductor material. For clarity, Integrated Circuit shall include charge-coupled devices (“CCDs”).

Bulk CMOS Information means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, and/or (ii) selected by Licensor either for incorporation into an Licensor Bulk CMOS process or otherwise pursuant to this agreement.

Industry Standard Information means those aspects of Background Know-How and Specific Results that are (i) directed to Lithography and BEOL, or (ii) applicable to Industry Standard CMOS and selected by Licensor either for incorporation into an Licensor Industry Standard CMOS process or otherwise selected pursuant to this agreement.

High Performance Device Information means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created on substrates, not including SOI Device Information. Bulk CMOS Information or Industry Standard Information.

SOI Device Information means Background Know-How and Specific Results pertaining to all process methods, steps, and structures created on commercially available SOI Wafers other than Bulk CMOS or Industry Standard Information.

Field of Use

This agreement pertains to the semiconductor industry.

License Grant

The Company grants for Permitted Applications only, a worldwide, nontransferable, and nonsublicensable right to use, sell and otherwise incorporate Mobility Technology, including Mobility Split Bridge(TM) Chips and current and future software drivers developed for Mobility Split Bridge(TM) Chips and owned by Mobility.

License Property

'Mobility Technology' shall mean all of Mobility's Split Bridge(TM) Technology (as hereinafter defined), including Mobility's current Split Bridge(TM) ASIC chip commonly known as 'Merlin' and ASIC Split Bridge(TM) chips currently under development by Mobility with LSI Logic or developed in the future ('Mobility Split Bridge(TM) Chips').

This further includes all related intellectual property and Mobility Split Bridge(TM) Chip intellectual property including without limitation software, patents (including, without limitation, the Patent Nos. 6,070,214 and 6,088,752) and patents pending, trade secrets, ASIC chips and related IP blocks, designs, specifications, and any future enhancements, modifications, variations thereto, and all intellectual property associated with the adaptation of cables and connectors adapted for use with Mobility's Split Bridge(TM) Chips and technology and future generations of any of the above .

'Split Bridge Technology' is the technology which allows a main computer PCI bus to be extended to a remote location by connecting two proprietary Mobility Split Bridge(TM) Chips with a high speed cable, and includes all of the above.  Mobility Technology does not include any incorporated 2C Technology.

'Split Bridge(TM) LINK' shall mean two Mobility Split Bridge(TM) Chips, associated connectors, and associated high speed cable which permit the use and implementation of Mobility Technology.

License Grant

For the Technology Licensor grants a non-exclusive, non-transferable, worldwide right and license under all of Licensors copyright, patent, trade secret, mask work, know how and other intellectual property rights in the Licensed Technology
– to design and develop, and engage Contractors to design and develop, modifications to and derivatives of the Licensed Technology for the purpose of creating Licensed Chips
– to use and engage third-party contractors to use the Licensed Technology, including such modifications and derivatives, in the design and development of Licensed Chips; and
– to manufacture, have manufactured, sell and otherwise distribute Licensed Chips.

For the Trademark Licensor grants a non-exclusive, non-transferable, worldwide right and license to use Trademarks in Licensees marketing, sale and distribution of Licensed Chips.

License Property

Licensor develops video processing and image enhancement technologies and designs, develops and manufactures products, including integrated circuits, for video applications.

'Trademarks' means Faroudjas logos and other trademarks as such marks vary in appearance and/or style from time to time.

The Parties are interested in working together to combine Licenor video processing and image enhancement technologies and expertise with Licenee's ASIC design and fabrication and display controller technologies and expertise, to provide reasonably priced, high-quality chip solutions for manufacturers of flat panel displays and other display devices.

Field of Use

Licensee intend to incorporate Licensor's technologies into our proprietary display processing solutions to create a video solution for the mass television market by combining Licensor's decoding, deinterlacing and image algorithms with our technology.

Licensee designs, develops, manufactures and markets application specific integrated circuits primarily for the flat panel display market.

License Grant

Licensor desires to grant to Licensee a license to use and to grant sublicenses to use GECKO to develop silicon-based products.

Licensor  hereby grants to Licensee a non-exclusive, nontransferable, worldwide license to use, duplicate, distribute, modify and enhance GECKO and the Documentation, solely for the development, manufacture and distribution of GECKO Products and GECKO Derivative Works.

Licensor hereby grants to Licensee the exclusive right to distribute and sell single chip MPEG 2 real time encoders developed by Licensee and/or its sublicensees using GECKO.

License Property

The term 'GECKO Products' shall mean silicon products (including the microcode, in object code form only, and documentation necessary to use such silicon products in Systems).

'GECKO' is video compression chip which is the subject of docket numbers 2056 and 2057 for patent applications.

GECKO

A. SPECIFICATIONS Document referred to as 'GECKO Design Specification.' Represented by the frame readable document named 'gecko.1.3.'

B. C-MODEL SOURCE CODE The code represented on pages 11-19 of the attached 30-page 'LIST OF FILES.' The C-Model Source Code performs software simulation for encoding, decoding, and other functions with the GECKO hardware.

C. VERILOG SOURCE CODE The code represented on pages 1-11 of the attached 'LIST OF FILES.' The Verilog Source Code represents the logical structure of the GECKO modules in source code format.

D. SIMULATION ENVIRONMENT All test benches/simulation suites used to stimulate the GECKO design in either behavioral or gate level verification. These test benches consist of Verilog or C-Model or other modules used for stimulation or verification of the design. These files can be found on pages 1-11 in the attached 'LIST OF FILES.'

E. MICROCODE The code I) required to exercise the design for the purpose of design verification; ii) required to enable the GECKO chip to perform any and all functions pursuant to its design. This microcode is represented by the '.asm' files on pages 1-2 of the attached 'LIST OF FILES,' including the 'assemble.c' file.

F. SYNTHESIS AND SIMULATION WITH IBM LIBRARY I) Gate-level libraries for IBM process represented on pages 27 and 28 of the attached 'LIST OF FILES.' ii) Synopsis scripts necessary for module and top-level synthesis to generate gate-level netlists. These are represented on pages 19-24 of the attached 'LIST OF FILES.'

G. NETLIST Gate-level netlist generated using IBM libraries.

H. IBM MASK Ultimate physical representation of the final device.

I. IBM SILICON The final GECKO integrated circuit in wafer, bare die, or packaged form.

Field of Use

The term of the license is in perpetuity.